Table of Contents
What are the things to be checked before placement stage?
Things to be checked before placement
- Check for any missing/extra placement & routing blockages.
- Don’t use cell list and whether it is properly applied in the tool.
- Don’t touch on cells and nets (make sure that, these are applied).
Why spare cells are used?
Use of Spare cells: Spare cells enable us to modify/improve the functionality of a chip with minimal changes in the mask. We can use already placed spare cells from the nearby location and just need to modify the metal interconnect. There is no need to make any changes in the base layers.
What are the different types of placement in VLSI?
Placement
- Pre-placement.
- Coarse placement (initial placement)
- Legalization.
- High Fanout Net Synthesis (HFNS)
- Placement optimizations.
- Area Recovery.
- Scan chain reordering.
What steps exactly tool does in the placement stage?
During initial placement, the tool focuses on the QOR for the function nets by ignoring the scan chains. After initial placement, the tool further improves the QOR by repartitioning and reordering the scan chains based on the initial placement. Scan chains reordering reduces wire length so timing will improve.
Why is CTS done before routing?
Clock is propagated before routing of signals nets and clock is the only signal nets switches frequently which act as sources for dynamic power dissipation.
What are spare cells?
Spare cells are basically elements embedded in the design which are not driving anything. The idea is that maybe they will enable an easy (metal) fix without the need of a full redesign.
What is eco VLSI?
Engineering Change Order or ECO in VLSI is the practice of introducing logic directly into the gate level netlist corresponding to a change that happens in the RTL. This owes to design mistake repairs or a change request from the customer.
What are the checks after CTS?
CTS Quality Checks
- Minimize Insertion Delay.
- Skew Balancing.
- Duty Cycle.
- Pulse Width.
- Clock Tree power consumption.
- Signal Integrity and Crosstalk.
What are placement blockages?
Placement blockages are used to: Reserve channels for buffer insertion. Prevent cells from being placed nearer to macros. Prevent congestion near macros.
What is Halo in VLSI?
Halo. Halos are blockages which is used around the macros to prevent congestion in later stages. If we move macro, halos move with it. Routing Halos can prevent signal integrity issues around blocks. Adding routing halos prevent long wires from being routed within the halo region.
What is pre CTS and post CTS?
It is quite apt to say that backend cycle also consists of two sub-processes – i) Before clock tree has been implemented, also known as pre-clock tree synthesis (CTS) stages; and ii) After clock tree has been implemented (post-CTS stages).
What are DRC checks in VLSI?
Design rule checks are nothing but physical checks of metal width, pitch and spacing requirement for the different layers which depend on different technology nodes.
What is spare cells in physical design?
Why end cap cells are used?
The end cap cells are placed in the design because of the following reasons: To protect the gate of a standard cell placed near the boundary from damage during manufacturing. To avoid the base layer DRC (Nwell and Implant layer) at the boundary. To make the proper alignment with the other block.
What is LVS check in VLSI?
Definition. Layout Versus Schematic (LVS) checking compares the extracted netlist from the layout to the original schematic netlist to determine if they match. The comparison check is considered clean if all the devices and nets of the schematic match the devices and the nets of the layout.
What is tweaker VLSI?
As an ECO tool, Tweaker optimizes a design incrementally and locally, with minimal impact to the existing performance. In all of the ECO fixing operations, Tweaker only focuses on only critical portions of a design, known as the “ECO Domain”.
What is the difference between HFNS and CTS?
Difference between HFNS and CTS? HFNS (High Fanout Net Synthesis) used in placement stage which uses buffers and inverters of relaxed rise and fall times. But in CTS (Clock Tree Synthesis), buffers and inverters of equal rise and fall times are used. NDR rules are also used for clock tree routing.
What is difference between Halo and blockage?
HALO ( Keep-Out Region): Halos of two adjacent macros can be overlap. If the macros are moved from one place to another place, Halos will also be moved. But in the case of blockages if the macros are moved from one place to another place the blockages cannot be moved.
How to add spare cells to the netlist in placement stage?
The inputs are tied to power or ground nets, as floating gates shouldn’t be allowed in the layout. The outputs are left unconnected. Use a command provided by the PnR tool to add the spare cells to the netlist in placement stage. An example using ICCompiler command is given below.
How do you arrange spare cells in a cell layout?
Sprinkle the individual spare cells in your layout, so from any point you may have a reasonably close library cell. Group the spare cells in multiple groups and sprinkle/place each group in the layout.
How to optimize PNR tool to optimize the spare cells?
Group the spare cells in multiple groups and sprinkle/place each group in the layout. If the spare cells are included in the netlist, you need to set an attribute `spare_cell` so that the PnR tool does no optimize these. If you do not set them as `spare_cell` or set a `dont_touch`, you will find that after placement all spare cells are gone.
What is the difference between metal mask and spare cell?
The metal connections have changed, and hence only metal masks are regenerated for the next fabrication. Spare cells need to added while the initial implementation. There are two ways to do this.